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Copyright (C) 2003-2004 mitsuman(mnishibe at ertl.jp) All Rights Reserved.
750k+
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verilog_mul 32 16 16
verilog_mul 60 53 53
verilog_mul 60 53 53 56
verilog_mul 32 16 16 0 512
verilog_mul 56 32 24 32
vcs test_mac56_32x24.v -R
(verilogXLなら verilog test_mac56_32x24.v)
Parsing design file 'test_mac56_32x24.v'
Parsing included file 'mac56_32x24.v'.
Back to file 'test_mac56_32x24.v'.
Top Level Modules:
test
TimeScale is 1 ns / 1 ns
1 of 10 unique modules to generate
1 of 1 modules done
Invoking loader...
Warning : License for product VCSRuntime_Net(725) will expire within9 days, on: 31-mar-2003.
If you would like to temporarily disable this message, set
the VCS_LIC_EXPIRE_WARNING environment variable to the number of days
before expiration that you want this message to start (the minimum is 5).
Chronologic VCS simulator copyright 1991-2000
Contains Synopsys proprietary information.
Compiler version 5.2; Runtime version 5.2; Mar 22 16:37 2003
c83fa926 * aedba7 + e40146c0 = 6cc85ccf0ed9ca(6cc85ccf0ed9ca) 0(-)
963e2b1e * 2e88ff + e8255721 = 0374e98f38e2e2(0374e98f38e2e2) 0(-)
4b0d76b6 * 46fd01 + b0564438 = c5261f472354b6(c5261f472354b6) 0(-)
9e63bd4c * b4da7b + de495f1a = 4e2ead3c8eab84(4e2ead3c8eab84) 0(-)
23a58d0d * 606da4 + debbc0a3 = ec2919dafce554(ec2919dafce554) 0(-)
98b09891 * 593ba2 + f03e154e = 25770bab52f6c2(25770bab52f6c2) 0(-)
6ae2a8c5 * f2bf98 + 37ea7e33 = 9d44c04fb92ff8(9d44c04fb92ff8) 0(-)
a52f3158 * 9cb68d + 79bebe52 = dedd4aebb2bd78(dedd4aebb2bd78) 0(-)
8dd63879 * 2e2ea3 + 17ddbf08 = 317413fb49b30b(317413fb49b30b) 0(-)
316b393e * 4c0d39 + 01de0c2a = 108c6e9b2fe4ce(108c6e9b2fe4ce) 0(-)
381ad91d * 7cd29f + cbd087ca = e72bb1d2d2a303(e72bb1d2d2a303) 0(-)
6b0df531 * ac18ad + 6c38444a = b42ff6ae574a1d(b42ff6ae574a1d) 0(-)
8b484390 * 435534 + 5a05f8ab = 7ea83da2cc8940(7ea83da2cc8940) 0(-)
5aa3ec34 * 09ff32 + bc411845 = bfcb368f1fee28(bfcb368f1fee28) 0(-)
f29158a2 * 8ea844 + e956d5e5 = 7082e4dfa1db08(7082e4dfa1db08) 0(-)
3f0b17f0 * 4a8176 + 1af20961 = 2d4b1ff28cf8a0(2d4b1ff28cf8a0) 0(-)
0a7e3632 * 794765 + f4170b47 = f90fa009753fba(f90fa009753fba) 0(-)
3145092d * c2bcd9 + 9c8e67c6 = c20911305bd325(c20911305bd325) 0(-)
67c3b724 * 7ec623 + 765e496a = a9c0ed1d1fe1ec(a9c0ed1d1fe1ec) 0(-)
1f79ed9b * 2d092a + c134f395 = c6be82cc9a6e6e(c6be82cc9a6e6e) 0(-)
5e893efb * 9d18d4 + fd93a2a2 = 3796f9697eafdc(3796f9697eafdc) 0(-)
0469aaca * 823efd + ec32d28e = ee71913c5eb5a2(ee71913c5eb5a2) 0(-)
e9ae7ed8 * 4ceff6 + 7a189963 = c0537181398b90(c0537181398b90) 0(-)
9788d167 * abd632 + 71dfdcf8 = d7970acf92001e(d7970acf92001e) 0(-)
6ed6e126 * a1fb75 + 16db57a3 = 5cfd5a92db285e(5cfd5a92db285e) 0(-)
d594a1a4 * 7d3952 + 2d797215 = 95f2d783ad4a88(95f2d783ad4a88) 0(-)
09e0667b * 9869b7 + 2cf57bb9 = 32d6ccab79b4ed(32d6ccab79b4ed) 0(-)
fd1486d0 * 71d6bd + 2bf5eb4a = 9c8044cca96790(9c8044cca96790) 0(-)
54d4b8b0 * 6f8c92 + 5d6d985a = 82646924a19460(82646924a19460) 0(-)
aadeda49 * d25751 + 39afb7b3 = c614ce8f93e019(c614ce8f93e019) 0(-)
a18acde1 * c0a582 + 20c911b2 = 9a599c99ee9142(9a599c99ee9142) 0(-)
2bd5c6ea * a367d9 + 559ae897 = 7195ce693bc25a(7195ce693bc25a) 0(-)
$finish at simulation time 320
V C S S i m u l a t i o n R e p o r t
Time: 320 ns
verilog_mul 38 32 24 32
Csa32 csa12( w50[31:0],w51[31:0], {3'b0,w36[28:0]},{w38[31:0]},{w39[30:0],1'b0} );
750k+