// Verilog : 32x24[bits] Multiplier
//  generated by Multiplier Generator
//  Copyright 2003 Mitsuru Nishibe (Takagi Lab.)


module mac56_32x24( out,in1,in2,in3 );
	output [55:0] out;
	input  [31:0] in1;
	input  [23:0] in2;
	input  [31:0] in3;

	wire [ 31:0]w0;  //  31, 32
	wire [ 31:0]w1;  //  32, 32
	wire [ 31:0]w2;  //  33, 32
	wire [ 31:0]w3;  //  34, 32
	wire [ 31:0]w4;  //  35, 32
	wire [ 31:0]w5;  //  36, 32
	wire [ 31:0]w6;  //  37, 32
	wire [ 31:0]w7;  //  38, 32
	wire [ 31:0]w8;  //  39, 32
	wire [ 31:0]w9;  //  40, 32
	wire [ 31:0]w10;  //  41, 32
	wire [ 31:0]w11;  //  42, 32
	wire [ 31:0]w12;  //  43, 32
	wire [ 31:0]w13;  //  44, 32
	wire [ 31:0]w14;  //  45, 32
	wire [ 31:0]w15;  //  46, 32
	wire [ 31:0]w16;  //  47, 32
	wire [ 31:0]w17;  //  48, 32
	wire [ 31:0]w18;  //  49, 32
	wire [ 31:0]w19;  //  50, 32
	wire [ 31:0]w20;  //  51, 32
	wire [ 31:0]w21;  //  52, 32
	wire [ 31:0]w22;  //  53, 32
	wire [ 31:0]w23;  //  54, 32
	wire [ 31:0]w24;  //  55, 32
	wire [ 33:0]w25;  //  33, 34
	wire [ 31:0]w26;  //  33, 32
	wire [ 33:0]w27;  //  36, 34
	wire [ 31:0]w28;  //  36, 32
	wire [ 33:0]w29;  //  39, 34
	wire [ 31:0]w30;  //  39, 32
	wire [ 33:0]w31;  //  42, 34
	wire [ 31:0]w32;  //  42, 32
	wire [ 33:0]w33;  //  45, 34
	wire [ 31:0]w34;  //  45, 32
	wire [ 33:0]w35;  //  48, 34
	wire [ 31:0]w36;  //  48, 32
	wire [ 33:0]w37;  //  51, 34
	wire [ 31:0]w38;  //  51, 32
	wire [ 33:0]w39;  //  54, 34
	wire [ 31:0]w40;  //  54, 32
	wire [ 36:0]w42;  //  36, 37
	wire [ 31:0]w43;  //  34, 32
	wire [ 34:0]w44;  //  39, 35
	wire [ 33:0]w45;  //  40, 34
	wire [ 36:0]w46;  //  45, 37
	wire [ 31:0]w47;  //  43, 32
	wire [ 34:0]w48;  //  48, 35
	wire [ 33:0]w49;  //  49, 34
	wire [ 36:0]w50;  //  54, 37
	wire [ 31:0]w51;  //  52, 32
	wire [ 39:0]w54;  //  39, 40
	wire [ 33:0]w55;  //  37, 34
	wire [ 38:0]w56;  //  45, 39
	wire [ 34:0]w57;  //  44, 35
	wire [ 40:0]w58;  //  54, 41
	wire [ 33:0]w59;  //  50, 34
	wire [ 34:0]w60;  //  55, 35
	wire [ 31:0]w61;  //  55, 32
	wire [ 45:0]w62;  //  45, 46
	wire [ 35:0]w63;  //  40, 36
	wire [ 44:0]w64;  //  54, 45
	wire [ 36:0]w65;  //  51, 37
	wire [ 54:0]w68;  //  54, 55
	wire [ 40:0]w69;  //  46, 41
	wire [ 40:0]w70;  //  55, 41
	wire [ 34:0]w71;  //  56, 35
	wire [ 55:0]w72;  //  55, 56
	wire [ 48:0]w73;  //  55, 49
	wire [ 56:0]w75;  //  56, 57
	wire [ 48:0]w76;  //  56, 49

	assign w0 = (in2[0]==1) ? in1[ 31:  0] : 0;
	assign w1 = (in2[1]==1) ? in1[ 31:  0] : 0;
	assign w2 = (in2[2]==1) ? in1[ 31:  0] : 0;
	assign w3 = (in2[3]==1) ? in1[ 31:  0] : 0;
	assign w4 = (in2[4]==1) ? in1[ 31:  0] : 0;
	assign w5 = (in2[5]==1) ? in1[ 31:  0] : 0;
	assign w6 = (in2[6]==1) ? in1[ 31:  0] : 0;
	assign w7 = (in2[7]==1) ? in1[ 31:  0] : 0;
	assign w8 = (in2[8]==1) ? in1[ 31:  0] : 0;
	assign w9 = (in2[9]==1) ? in1[ 31:  0] : 0;
	assign w10 = (in2[10]==1) ? in1[ 31:  0] : 0;
	assign w11 = (in2[11]==1) ? in1[ 31:  0] : 0;
	assign w12 = (in2[12]==1) ? in1[ 31:  0] : 0;
	assign w13 = (in2[13]==1) ? in1[ 31:  0] : 0;
	assign w14 = (in2[14]==1) ? in1[ 31:  0] : 0;
	assign w15 = (in2[15]==1) ? in1[ 31:  0] : 0;
	assign w16 = (in2[16]==1) ? in1[ 31:  0] : 0;
	assign w17 = (in2[17]==1) ? in1[ 31:  0] : 0;
	assign w18 = (in2[18]==1) ? in1[ 31:  0] : 0;
	assign w19 = (in2[19]==1) ? in1[ 31:  0] : 0;
	assign w20 = (in2[20]==1) ? in1[ 31:  0] : 0;
	assign w21 = (in2[21]==1) ? in1[ 31:  0] : 0;
	assign w22 = (in2[22]==1) ? in1[ 31:  0] : 0;
	assign w23 = (in2[23]==1) ? in1[ 31:  0] : 0;

	assign w24 = in3;

	// LAYER-0
	assign w25[33:33]=w2[31:31] , w25[0:0]=w0[0:0];
	Csa32 csa0( w25[32:1],w26[31:0], {1'b0,w0[31:1]},{w1[31:0]},{w2[30:0],1'b0} );
	assign w27[33:33]=w5[31:31] , w27[0:0]=w3[0:0];
	Csa32 csa1( w27[32:1],w28[31:0], {1'b0,w3[31:1]},{w4[31:0]},{w5[30:0],1'b0} );
	assign w29[33:33]=w8[31:31] , w29[0:0]=w6[0:0];
	Csa32 csa2( w29[32:1],w30[31:0], {1'b0,w6[31:1]},{w7[31:0]},{w8[30:0],1'b0} );
	assign w31[33:33]=w11[31:31] , w31[0:0]=w9[0:0];
	Csa32 csa3( w31[32:1],w32[31:0], {1'b0,w9[31:1]},{w10[31:0]},{w11[30:0],1'b0} );
	assign w33[33:33]=w14[31:31] , w33[0:0]=w12[0:0];
	Csa32 csa4( w33[32:1],w34[31:0], {1'b0,w12[31:1]},{w13[31:0]},{w14[30:0],1'b0} );
	assign w35[33:33]=w17[31:31] , w35[0:0]=w15[0:0];
	Csa32 csa5( w35[32:1],w36[31:0], {1'b0,w15[31:1]},{w16[31:0]},{w17[30:0],1'b0} );
	assign w37[33:33]=w20[31:31] , w37[0:0]=w18[0:0];
	Csa32 csa6( w37[32:1],w38[31:0], {1'b0,w18[31:1]},{w19[31:0]},{w20[30:0],1'b0} );
	assign w39[33:33]=w23[31:31] , w39[0:0]=w21[0:0];
	Csa32 csa7( w39[32:1],w40[31:0], {1'b0,w21[31:1]},{w22[31:0]},{w23[30:0],1'b0} );

	// LAYER-1
	assign w42[36:34]=w27[33:31] , w42[1:0]=w25[1:0];
	Csa32 csa8( w42[33:2],w43[31:0], {w25[33:2]},{w26[31:0]},{w27[30:0],1'b0} );
	assign w44[0:0]=w28[0:0];
	Csa34 csa9( w44[34:1],w45[33:0], {3'b0,w28[31:1]},{w29[33:0]},{w30[31:0],2'b0} );
	assign w46[36:34]=w33[33:31] , w46[1:0]=w31[1:0];
	Csa32 csa10( w46[33:2],w47[31:0], {w31[33:2]},{w32[31:0]},{w33[30:0],1'b0} );
	assign w48[0:0]=w34[0:0];
	Csa34 csa11( w48[34:1],w49[33:0], {3'b0,w34[31:1]},{w35[33:0]},{w36[31:0],2'b0} );
	assign w50[36:34]=w39[33:31] , w50[1:0]=w37[1:0];
	Csa32 csa12( w50[33:2],w51[31:0], {w37[33:2]},{w38[31:0]},{w39[30:0],1'b0} );

	// LAYER-2
	assign w54[39:37]=w44[34:32] , w54[2:0]=w42[2:0];
	Csa34 csa13( w54[36:3],w55[33:0], {w42[36:3]},{2'b0,w43[31:0]},{w44[31:0],2'b0} );
	assign w56[38:37]=w46[36:35] , w56[1:0]=w45[1:0];
	Csa35 csa14( w56[36:2],w57[34:0], {3'b0,w45[33:2]},{w46[34:0]},{w47[31:0],3'b0} );
	assign w58[40:36]=w50[36:32] , w58[1:0]=w48[1:0];
	Csa34 csa15( w58[35:2],w59[33:0], {1'b0,w48[34:2]},{w49[33:0]},{w50[31:0],2'b0} );
	assign w60[34:34]=w24[31:31] , w60[1:0]=w51[1:0];
	Csa32 csa16( w60[33:2],w61[31:0], {2'b0,w51[31:2]},{w40[31:0]},{w24[30:0],1'b0} );

	// LAYER-3
	assign w62[45:40]=w56[38:33] , w62[3:0]=w54[3:0];
	Csa36 csa17( w62[39:4],w63[35:0], {w54[39:4]},{2'b0,w55[33:0]},{w56[32:0],3'b0} );
	assign w64[44:41]=w58[40:37] , w64[3:0]=w57[3:0];
	Csa37 csa18( w64[40:4],w65[36:0], {6'b0,w57[34:4]},{w58[36:0]},{w59[33:0],3'b0} );

	// LAYER-4
	assign w68[54:46]=w64[44:36] , w68[4:0]=w62[4:0];
	Csa41 csa19( w68[45:5],w69[40:0], {w62[45:5]},{5'b0,w63[35:0]},{w64[35:0],5'b0} );
	assign w70[5:0]=w65[5:0];
	Csa35 csa20( w70[40:6],w71[34:0], {4'b0,w65[36:6]},{w60[34:0]},{w61[31:0],3'b0} );

	// LAYER-5
	assign w72[55:55]=w70[40:40] , w72[5:0]=w68[5:0];
	Csa49 csa21( w72[54:6],w73[48:0], {w68[54:6]},{8'b0,w69[40:0]},{w70[39:0],9'b0} );

	// LAYER-6
	assign w75[56:56]=w71[34:34] , w75[6:0]=w72[6:0];
	Csa49 csa22( w75[55:7],w76[48:0], {w72[55:7]},{w73[48:0]},{w71[33:0],15'b0} );

	// LAYER-LAST
	Cla56 cla(out, {w75[55:0]},{w76[47:0],8'b0});

endmodule

module Csa32(out1,out2,in1,in2,in3);
	input [31:0] in1,in2,in3;
	output [31:0] out1,out2;
	assign out1 = (in1^in2^in3);
	assign out2 = (in1&(in2|in3)|in2&in3);
endmodule

module Csa34(out1,out2,in1,in2,in3);
	input [33:0] in1,in2,in3;
	output [33:0] out1,out2;
	assign out1 = (in1^in2^in3);
	assign out2 = (in1&(in2|in3)|in2&in3);
endmodule

module Csa35(out1,out2,in1,in2,in3);
	input [34:0] in1,in2,in3;
	output [34:0] out1,out2;
	assign out1 = (in1^in2^in3);
	assign out2 = (in1&(in2|in3)|in2&in3);
endmodule

module Csa36(out1,out2,in1,in2,in3);
	input [35:0] in1,in2,in3;
	output [35:0] out1,out2;
	assign out1 = (in1^in2^in3);
	assign out2 = (in1&(in2|in3)|in2&in3);
endmodule

module Csa37(out1,out2,in1,in2,in3);
	input [36:0] in1,in2,in3;
	output [36:0] out1,out2;
	assign out1 = (in1^in2^in3);
	assign out2 = (in1&(in2|in3)|in2&in3);
endmodule

module Csa41(out1,out2,in1,in2,in3);
	input [40:0] in1,in2,in3;
	output [40:0] out1,out2;
	assign out1 = (in1^in2^in3);
	assign out2 = (in1&(in2|in3)|in2&in3);
endmodule

module Csa49(out1,out2,in1,in2,in3);
	input [48:0] in1,in2,in3;
	output [48:0] out1,out2;
	assign out1 = (in1^in2^in3);
	assign out2 = (in1&(in2|in3)|in2&in3);
endmodule

module Cla56(out,in1,in2);
	output [55:0] out;
	input  [55:0] in1,in2;
	assign out=in1+in2;
endmodule